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rev.2.2 _00 battery protection ic for 3-series or 4-series cell pack S-8204A series seiko instruments inc. 1 the S-8204A series includes a voltage detection circuit with high accuracy and a delay circuit, in single use, makes it possible for users to monitor the st atus of 3-series or 4-series cell lithium-ion rechargeable battery. by switching the voltage level which is applied to the sel pin, users are able to use this ic either for 3-series or 4-series cell pack. by cascade connection using this ic, it is also possible to protect 5-series or more cells *1 rechargeable lithium-ion battery pack. *1. refer to the usage guideline for connection examples of protection circuit with 5-series cell. ? features (1) high-accuracy voltage detection for each cell ? overcharge detection voltage n (n = 1 to 4) 3.8 v to 4.6 v (50 mv step) accuracy 25 mv ? overcharge release voltage n (n = 1 to 4) 3.6 v to 4.6 v *1 accuracy 50 mv ? overdischarge detection voltage n (n = 1 to 4) 2.0 v to 3.0 v (100 mv step) accuracy 80 mv ? overdischarge release voltage n (n = 1 to 4) 2.0 v to 3.4 v *2 accuracy 100 mv (2) discharge overcurrent detection in 3-step ? discharge overcurrent detection voltage 1 0.05 v to 0.30 v (50 mv step) accuracy 15 mv ? discharge overcurrent detection voltage 2 0.5 v (fixed) accuracy 100 mv ? short circuit detection volt age 1.0 v (fixed) accuracy 300 mv (3) charge overcurrent detection ? charge overcurrent detection voltage ? 0.25 v to ? 0.05 v (50 mv step) accuracy 30 mv (4) settable by external capacitor; overcharge detect ion delay time, overdischarge detection delay time, discharge overcurrent detection delay time 1, di scharge overcurrent detecti on delay time 2, charge overcurrent delay time (short circuit detection voltage delay time is internally fixed.) (5) switchable between 3-series and 4-series cell by using the sel pin (6) independent charging and dischar ge control by the control pins (7) withstand voltage element absolute maximum rating : 24 v (8) wide range of operation voltage 2 v to 22 v (9) wide range of operation temperature ? 40 c to + 85 c (10) low current consumption ? operation mode 33 a max. ( + 25 c) ? power-down mode 0.1 a max. ( + 25 c) (11) lead-free product *1. overcharge hysteresis voltage n (n = 1 to 4) is selectable in 0 v, or in 0.1 v to 0.4 v in 50 mv step. (overcharge hysteresis voltage = overcharge detection voltage ? overcharge release voltage) *2. overdischarge hysteresis voltage n (n = 1 to 4) is selectable in 0 v, or in 0.2 v to 0.7 v in 100 mv step. (overdischarge hysteresis voltage = overdischarge release voltage ? overdischarge detection voltage) ? applications ? rechargeable lithium-ion battery packs ? package drawing code package name package tape reel 16-pin tssop ft016-a ft016-a ft016-a
battery protection ic for 3-series or 4-series cell pack S-8204A series rev.2.2 _00 seiko instruments inc. 2 ? block diagram discharge overcurrent 2 over- charge 1 ove r - discharge 1 ove r - charge 2 over- discharge 2 ove r - charge 3 ove r - discharge 3 over- charge 4 ove r - discharge 4 discharge overcurrent 1 short circuit c harge overcurrent cop cit vmp dop vini cdt ? + control circuit delay circuit delay circuit delay circuit r vmd r vms cct sel delay circuit delay circuit ? + ? + ? + ? + ? + ? + ? + delay circuit + ? + ? + ? + ? ctlc ctld vdd vc1 vc2 vc3 vc4 vss remark diodes in the figure are parasitic diodes. figure 1
battery protection ic for 3-series or 4-series cell pack rev.2.2 _00 S-8204A series seiko instruments inc. 3 ? product name structure 1. product name S-8204A xx ? xxxx s package name (abbreviation) and packing specifications *1 tct1 : 16-pin tssop, tape serial code *2 sequentially set from aa to zz *1. refer to the tape specifications. *2. refer to ? 2. product name list ?. 2. product name list table 1 product name/ item overcharge detection voltage [v cu ] overcharge release voltage [v cl ] overdischarge detection voltage [v dl ] overdischarge release voltage [v du ] discharge overcurrent detection voltage 1 [v diov1 ] charge overcurrent detection voltage [v ciov ] 0 v battery charge function S-8204Aab- tct1s 4.350 0.025 v 4.150 0.050 v 2.00 0.080 v 2.70 0.100 v 0.25 0.015 v ? 0.10 0.030 v available S-8204Aac- tct1s 4.200 0.025 v 4.100 0.050 v 2.70 0.080 v 2.90 0.100 v 0.25 0.015 v ? 0.25 0.030 v available S-8204Aad- tct1s 3.800 0.025 v 3.600 0.050 v 2.00 0.080 v 2.30 0.100 v 0.30 0.015 v ? 0.25 0.030 v available S-8204Aae- tct1s 4.250 0.025 v 4.050 0.050 v 2.40 0.080 v 2.70 0.100 v 0.20 0.015 v ? 0.15 0.030 v unavailable remark please contact our sales office for products with detection voltage values other than those specified above.
battery protection ic for 3-series or 4-series cell pack S-8204A series rev.2.2 _00 seiko instruments inc. 4 ? pin configuration 16-pin tssop top view 8 7 6 5 3 2 4 1 11 16 9 10 12 14 15 13 cop vmp dop vini cdt cct cit sel ctlc ctld vdd vc1 vc2 vc3 vc4 vss figure 2 table 2 pin no. symbol description 1 cop fet gate connection pin for charge control (nch open drain output) 2 vmp pin for voltage detection between vdd and vmp 3 dop fet gate connection pin for discharge control fet (cmos output) pin for voltage detection between vss and vini 4 vini ? pin for discharge overcurrent detection 1,2/pin for short circuit detection voltage ? pin for charge overcurrent detection 5 cdt capacitor connection pin for delay for overdischarge detection voltage 6 cct capacitor connection pin for del ay for overcharge detection voltage 7 cit capacitor connection pin for delay detection for disc harge overcurrent 1, 2 for delay for charge overcurrent detection 8 sel pin for switching 3-series or 4-series cell ? v ss level: 3-series cell ? v dd level : 4-series cell 9 vss input pin for negative power supply, connection pin for battery 4?s negative voltage 10 vc4 connection pin for battery 4?s negative voltage 11 vc3 connection pin for battery 3?s negative voltage, connection pin for battery 4?s positive voltage 12 vc2 connection pin for battery 2?s negative voltage, connection pin for battery 3?s positive voltage 13 vc1 connection pin for battery 1?s negative voltage, connection pin for battery 2?s positive voltage 14 vdd input pin for positive power supply, connection pin for battery 1?s positive voltage 15 ctld control pin for discharge fet 16 ctlc control pin for charge fet
battery protection ic for 3-series or 4-series cell pack rev.2.2 _00 S-8204A series seiko instruments inc. 5 ? absolute maximum ratings table 3 (ta = 25 c unless otherwise specified) item symbol applied pin absolute maximum ratings unit input voltage between vdd and vss v ds ? v ss ? 0.3 to v ss + 24 v input pin voltage v in vc1, vc2, vc3, vc4, ctlc, ctld, sel, cct, cdt, cit, vini v ss ? 0.3 to v dd + 0.3 v vmp pin input voltage v vmp vmp v ss ? 0.3 to v ss + 24 v dop pin output voltage v dop dop v ss ? 0.3 to v dd + 0.3 v cop pin output voltage v cop cop v ss ? 0.3 to v ss + 24 v 400 (when not mounted on board) mw power dissipation p d ? 1100 *1 mw operating ambient temperature t opr ? ? 40 to + 85 c storage temperature t stg ? ? 40 to + 125 c *1. when mounted on board [mounted board] (1) board size : 114.3 mm 76.2 mm t1.6 mm (2) board name : jedec standard51-7 caution the absolute maximum ratings are rated values exceeding which the product could suffer physical damage. these values must therefore not be exceeded under any conditions. 0 50 100 150 800 400 0 power dissipation (p d ) [mw] ambient temperature (ta) [ c] 1000 600 200 1200 figure 3 power dissipation of package (when mounted on board)
battery protection ic for 3-series or 4-series cell pack S-8204A series rev.2.2 _00 seiko instruments inc. 6 ? electrical characteristics table 4 (1/2) (ta = 25 c unless otherwise specified) item symbol conditions mi n. typ. max. unit test circuit [ detection voltage ] overcharge detection voltage n (n = 1, 2, 3, 4) v cun 3.8 v to 4.6 v, adjustable 50 mv step v cun ? 0.025 v cun v cun + 0.025 v 2 overcharge release voltage n (n = 1, 2, 3, 4) v cln v cl v cu v cln ? 0.05 v cln v cln + 0.05 v 2 3.6 v to 4.6 v, adjustable 50 mv step v cl = v cu v cln ? 0.025 v cln v cln + 0.025 v 2 overdischarge detection voltage n (n = 1, 2, 3, 4) v dln 2.0 v to 3.0 v, adjustable 100 mv step v dln ? 0.08 v dln v dln + 0.08 v 2 overdischarge release voltage n (n = 1, 2, 3, 4) v dun v dl v du v dun ? 0.10 v dun v dun + 0.10 v 2 2.0 v to 3.4 v, adjustable 100 mv step v dl = v du v dun ? 0.08 v dun v dun + 0.08 v 2 discharge overcurrent detection voltage 1 v diov1 0.05 v to 0.30 v, adjustable v diov1 ? 0.015 v diov1 v diov1 + 0.015 v 2 discharge overcurrent detection voltage 2 v diov2 ? 0.4 0.5 0.6 v 2 short circuit detection voltage v short ? 0.7 1.0 1.3 v 2 charge overcurrent detection voltage v ciov ? 0.25 v to ? 0.05 v, adjustable v ciov ? 0.03 v ciov v ciov + 0.03 v 2 temperature coefficient 1 *1 t coe1 ta = 0c to 50c *3 ? 1.0 0 1.0 mv/c 2 temperature coefficient 2 *2 t coe2 ta = 0c to 50c *3 ? 0.5 0 0.5 mv/c 2 [ delay time function ] *4 cct pin internal resistance r inc v1 = 4.7 v, v2 = v3 = v4 = 3.5 v 6.15 8.31 10.2 m ? 3 cdt pin internal resistance r ind v1 = 1.5 v, v2 = v3 = v4 = 3.5 v 615 831 1020 k ? 3 cit pin internal resistance 1 r ini1 v1 = v2 = v3 = v4 = 3.5 v 123 166 204 k ? 3 cit pin internal resistance 2 r ini2 v1 = v2 = v3 = v4 = 3.5 v 12.3 16.6 20.4 k ? 3 cct pin detection voltage v cct v ds = 15.2 v v1 = 4.7 v, v2 = v3 = v4 = 3.5 v v ds 0.68 v ds 0.70 v ds 0.72 v 3 cdt pin detection voltage v cdt v ds = 12.0 v v1 = 1.5 v, v2 = v3 = v4 = 3.5 v v ds 0.68 v ds 0.70 v ds 0.72 v 3 cit pin detection voltage v cit v ds = 14.0 v v1 = v2 = v3 = v4 = 3.5 v v ds 0.68 v ds 0.70 v ds 0.72 v 3 short circuit detection voltage delay time t short fet gate capacitance = 2000 pf 100 300 600 s 3 [ 0 v battery charge function ] charger voltage for start charging 0 v battery v 0cha available 0 v charging ? 0.8 1.5 v 4 battery voltage for inhibit charging 0 v battery v 0inh inhibit 0 v charging 0.4 0.7 1.1 v 4 [ internal resistance ] resistance between vmp and vdd r vmd ? 0.5 1 1.5 m ? 5 resistance between vmp and vss r vms ? 450 900 1800 k ? 5
battery protection ic for 3-series or 4-series cell pack rev.2.2 _00 S-8204A series seiko instruments inc. 7 table 4 (2/2) (ta = 25 c unless otherwise specified) item symbol conditions mi n. typ. max. unit test circuit [ input voltage ] operating voltage between vdd and vss v dsop fixed output voltage of dop and cop 2 ? 22 v 2 ctlc input voltage ?h? v ctlch v1 = v2 = v3 = v4 = 3.5 v ? ? 0.91 v 2 ctlc input voltage ?l? v ctlcl v1 = v2 = v3 = v4 = 3.5 v 0.59 ? ? v 2 ctld input voltage ?h? v ctldh v1 = v2 = v3 = v4 = 3.5 v ? ? 0.91 v 2 ctld input voltage ?l? v ctldl v1 = v2 = v3 = v4 = 3.5 v 0.59 ? ? v 2 sel input voltage ?h? v selh v ds = 14.0 v v1 = v2 = v3 = v4 = 3.5 v v ds 0.8 ? ? v 2 sel input voltage ?l? v sell v ds = 14.0 v v1 = v2 = v3 = v4 = 3.5 v ? ? v ds 0.2 v 2 [ input current ] current consumption during operation i ope v1 = v2 = v3 = v4 = 3.5 v ? 15 33 a 1 current consumption at power-down i pdn v1 = v2 = v3 = v4 = 1.5 v ? ? 0.1 a 1 vc1 pin current i vc1 v1 = v2 = v3 = v4 = 3.5 v ? 0.3 0 0.3 a 5 vc2 pin current i vc2 v1 = v2 = v3 = v4 = 3.5 v ? 0.3 0 0.3 a 5 vc3 pin current i vc3 v1 = v2 = v3 = v4 = 3.5 v ? 0.3 0 0.3 a 5 vc4 pin current i vc4 v1 = v2 = v3 = v4 = 3.5 v ? 6.0 ? 3.0 ? 0.5 a 5 ctlc pin current ?h? i ctlch v1 = v2 = v3 = v4 = 3.5 v, maximum current flowing into ctlc pin 3.0 10.0 20.0 a 5 ctlc pin current ?l? i ctlcl v1 = v2 = v3 = v4 = 3.5 v, v ctlc = v ss ? 0.8 ? 0.6 ? 0.4 a 5 ctld pin current ?h? i ctldh v1 = v2 = v3 = v4 = 3.5 v, maximum current flowing into ctld pin 3.0 10.0 20.0 a 5 ctld pin current ?l? i ctldl v1 = v2 = v3 = v4 = 3.5 v, v ctld = v ss ? 0.8 ? 0.6 ? 0.4 a 5 sel pin current ?h? i selh v1 = v2 = v3 = v4 = 3.5 v, v sel = v dd ? ? 0.1 a 5 sel pin current ?l? i sell v1 = v2 = v3 = v4 = 3.5 v, v sel = v ss ? 0.1 ? ? a 5 [ output current ] cop pin leakage current i coh v cop = 22 v ? ? 0.1 a 5 cop pin sink current i col v cop = v ss + 0.5 v 10 ? ? a 5 dop pin source current i doh v dop = v dd ? 0.5 v 10 ? ? a 5 dop pin sink current i dol v dop = v ss + 0.5 v 10 ? ? a 5 *1. voltage temperature coefficient 1 : overcharge detection voltage *2. voltage temperature coefficient 2 : di scharge overcurrent detection voltage 1 *3. since products are not screened at high and low temperat ure, the specification for this temperature range is guaranteed by design, not tested in production. *4. delay time function is described in ? ? operation ? in detail.
battery protection ic for 3-series or 4-series cell pack S-8204A series rev.2.2 _00 seiko instruments inc. 8 ? test circuit in this chapter, describing how to test the S-8204A series . in case of selecting to use it for 4-series cell battery, set sel pin = v dd level. for 3-series cell battery, set sel pin = v ss level and short between vc3 and vc4 pin. 1. current consumption during operation and power-down (test circuit 1) 1. 1 current consumption during operation (i ope ) the current at the vss pin when v1 = v2 = v3 = v4 = 3.5 v and v vmp = v dd is the current consumption during operation (i ope ). 1. 2 current consumption at power-down (i pdn ) the current at the vss pin when v1 = v2 = v3 = v4 = 1.5 v and v vmp = v ss is the current consumption at power-down (i pdn ). 2. overcharge detection voltage, overcharge release voltage, overdischarge detection voltage, overdischarge release voltage, discharge overcurrent detection voltage 1, discharge overcurrent detection voltage 2, short circuit de tection voltage, charge overcurrent detection voltage, ctlc input voltage ?h?, ctlc input vo ltage ?l?, ctld input voltage ?h?, ctld input voltage ?l?, sel input voltage ?h?, sel input voltage ?l? (test circuit 2) confirm both cop and dop pins are in ?l? (its voltage level is v ds 0.1 v or less) after setting v vmp = v sel = v dd , v vini = v ctlc = v ctld = v ss , cct pin = open, cdt pin = open, cit pin = open, v1 = v2 = v3 = v4 = 3.5 v. (this status is referred to as initial state.) 2. 1 overcharge detection voltage (v cu1 ), overcharge release voltage (v cl1 ) the overcharge detection voltage (v cu1 ) is a voltage at v1; when the cop pin?s voltage is set to ?h? (its voltage level is v ds 0.9 v or more) after increasing a voltage at v1 gradually from the initial state. after that, decreasing a voltage at v1 gradually, a vo ltage at v1 when the cop pin?s voltage is set to ?l?; is the overcharge release voltage (v cl1 ). 2. 2 overdischarge detection voltage (v dl1 ), overdischarge release voltage (v du1 ) the overdischarge detection voltage (v dl1 ) is a voltage at v1; when the dop pin?s voltage is set to ?h? after decreasing a voltage at v1 gradually from the in itial state. after that, increasing a voltage at v1 gradually, a voltage at v1 when the dop pin?s volt age is set to ?l?; is the overdischarge release voltage (v du1 ). by changing the voltage at vn (n = 2 to 4), user s can define the overcharge detection voltage (v cun ), the overcharge release voltage (v cln ), the overdischarge detection voltage (v dln ), the overdischarge release voltage (v dun ) as well when n = 1. 2. 3 discharge overcurrent detection voltage 1 (v diov1 ) the discharge overcurrent detection voltage 1 (v diov1 ) is the vini pin?s voltage; when the dop pin?s voltage is set to ?h? after increasing the vini pin?s voltage gradually from the initial status. 2. 4 discharge overcurrent detection voltage 2 (v diov2 ) the discharge overcurrent detection voltage 2 (v diov2 ) is a voltage at the vini pin; when a flowing current from the cit pin reaches 500 a or more after increasing the vini pin?s voltage gradually from the initial status.
battery protection ic for 3-series or 4-series cell pack rev.2.2 _00 S-8204A series seiko instruments inc. 9 2. 5 short circuit detection voltage (v short ) the short circuit detection voltage (v short ) is the vini pin?s voltage; when the dop pin?s voltage is set to ?h? after increasing the vini pin?s voltage gradually from the initial state after setting the cit pin?s voltage to the v ss level. 2. 6 charge overcurrent detection voltage (v ciov ) the charge overcurrent detection voltage (v ciov ) is the vini pin?s voltage; when the cop pin?s voltage is set to ?h? after decreasing the vini pin? s voltage gradually from the initial status. 2. 7 ctlc input voltage ?h? (v ctlch ), ctlc input voltage ?l? (v ctlcl ) the ctlc input voltage ?h? (v ctlch ) is the ctlc pin?s voltage; when the cop pin?s voltage is set to ?h? after increasing the ctlc pin?s voltage gradually fr om the initial status. after that, decreasing the ctlc pin?s voltage gradually, the ctlc pin?s voltage when the cop pin?s voltage is set to ?l?; is the ctlc input voltage ?l? (v ctlcl ). 2. 8 ctld input voltage ?h? (v ctldh ), ctld input voltage ?l? (v ctldl ) the ctld input voltage ?h? (v ctldh ) is the ctld pin?s voltage; when the dop pin?s voltage is set to ?h? after increasing the ctld pin?s voltage gradually from the initial state. after that, decreasing the ctld pin?s voltage gradually, the ctld pin?s voltage when the dop pin?s voltage is set to ?l?; is the ctld input voltage ?l? (v ctldl ). 2. 9 sel input voltage ?h? (v selh ), sel input voltage ?l? (v sell ) start from the initial status, set v4 = 0 v. confir m the dop is in ?h?. after that, decreasing the sel pin?s voltage gradually, the sel pin?s voltage when the dop pin?s voltage is set to ?l?; is the sel input voltage ?l? (v sell ). after that, increasing the sel pin?s voltage gradually, the sel pin?s voltage when the dop pin?s voltage is set to ?h?; is the sel input voltage ?h? (v selh ). 3. cct pin internal resistance, cdt pin internal r esistance, cit pin internal resistance 1, cit pin internal resistance 2, cct pin detection voltage, cdt pin detection voltage, cit pin detection voltage, short circuit detection voltage delay time (test circuit 3) confirm both cop and dop pins are in ?l? after setting v vmp = v sel = v dd , v vini = v ctlc = v ctld = cct = cdt = cit = v ss , v1 = v2 = v3 = v4 = 3.5 v. (this status is referred to as initial state.) 3. 1 cct pin internal resistance (r inc ) the cct pin internal resistance (r inc ) is r inc = v ds / i cct , i cct is the current which flows from the cct pin when setting v1 = 4.7 v from the initial status. 3. 2 cdt pin internal resistance (r ind ) the cdt pin internal resistance (r ind ) is r ind = v ds / i cdt , i cdt is the current which flows from the cdt pin when setting v1 = 1.5 v from the initial status. 3. 3 cit pin internal resistance 1 (r ini1 ) the cit pin internal resistance 1 (r ini1 ) is r ini1 = v ds / i cit1 , i cit1 is the current which flows from the cit pin when setting v vini = v diov1 max. + 0.05 v from the initial status. 3. 4 cit pin internal resistance 2 (r ini2 ) the cit pin internal resistance 2 (r ini2 ) is r ini2 = v ds / i cit2 , i cit2 is the current which flows from the cit pin when setting v vini = v diov2 max. + 0.05 v from the initial status.
battery protection ic for 3-series or 4-series cell pack S-8204A series rev.2.2 _00 seiko instruments inc. 10 3. 5 cct pin detection voltage (v cct ) the cct pin detection voltage (v cct ) is the voltage at the cct pin when the cop pin?s voltage is set to ?h? (voltage v ds 0.9 v or more) after increasing the cct pin?s voltage gradually, after setting v1 = 4.7 v from the initial state. 3. 6 cdt pin detection voltage (v cdt ) the cdt pin detection voltage (v cdt ) is the voltage at the cdt pin when the dop pin?s voltage is set to ?h? (voltage v ds 0.9 v or more) after increasing the cdt pin?s voltage gradually, after setting v1 = 1.5 v from the initial state. 3. 7 cit pin detection voltage (v cit ) the cit pin detection voltage (v cit ) is the voltage at the cit pin when the dop pin?s voltage is set to ?h? (voltage v ds 0.9 v or more) after increasing the cit pin?s voltage gradually, after setting v vini = v diov1 max. + 0.05 v from the initial state. 3. 8 short circuit detection voltage delay time (t short ) short circuit detection voltage delay time (t short ) is a period in which the dop pin?s voltage changes from ?l? to ?h? by changing the dop pin?s volta ge instantaneously from the initial state to v short max.+ 0.05 v. 4. charger voltage for start charging 0 v battery, battery voltage for inhibit charging 0 v battery (test circuit 4) according to user?s selection of the function to char ge 0 v battery, either function of charger voltage for start charging 0 v battery or battery voltage for inhi bit charging 0 v battery is applied to each product. 4. 1 charger voltage for start charging 0 v battery (v 0cha ) (product with function to charge 0v battery) in this charger voltage for start charging 0v battery, when v1 = v2 = v3 = v4 = 0 v, v vmp = v 0cha max., the cop pin?s voltage is v 0cha max. ? 1 v or less. 4. 2 battery voltage for inhibit charging 0 v battery (v 0inh ) (product with function to inhibit charging 0v battery) in this battery voltage for inhibit charging 0 v battery, when v1 = v2 = v3 = v4 = v 0inh min., v vmp = 22 v, the cop pin?s voltage is v vmp ? 1 v or more. 5. resistance between vmp and vd d, resistance between vmp and vss, vc1 pin current, vc2 pin current, vc3 pin current, vc4 pin current, ctlc pin current ?h?, ctlc pin current ?l?, ctld pin current ?h?, ctld pin current ?l?, sel pi n current ?h?, sel pin current ?l?, cop pin leakage current, cop pin sink current, dop pin source current, dop pin sink current (test circuit 5) set v vmp = v sel = v dd , v vini = v ctlc = v ctld = v ss , v1 = v2 = v3 = v4 = 3.5 v, set other pins open. (this status is referred to as initial state.) 5. 1 resistance between vmp and vdd (r vmd ) the value of resistance between vmp and vdd (r vmd ) can be defined by r vmd = v ds /i vmd by using the vmp pin?s current (i vmd ) when v vini = 1.5 v and v vmp = v ss after the initial status.
battery protection ic for 3-series or 4-series cell pack rev.2.2 _00 S-8204A series seiko instruments inc. 11 5. 2 resistance between vmp and vss (r vms ) the value of resistan ce between vmp and vss (r vms ) can be defined by r vms = v ds /i vms by using the vmp pin?s current (i vms ) when v1 = v2 = v3 = v4 = 1.8 v after the initial status. 5. 3 vc1 pin current (i vc1 ), vc2 pin current (i vc2 ), vc3 pin current (i vc3 ), vc4 pin current (i vc4 ) in the initial status, each current flows in the vc 1 pin, vc2 pin, vc3 pin, vc4 pin is the vc1 pin current (i vc1 ), the vc2 pin current (i vc2 ), the vc3 pin current (i vc3 ), the vc4 pin current (i vc4 ), respectively. 5. 4 ctlc pin current ?h? (i ctlch ), ctlc pin current ?l? (i ctlcl ) the current which flows in the ctlc pin at the initial status is the ctlc pin current ?l? (i ctlcl ). after that, increasing the ctlc pin?s voltage gradually, the maximum current which flows in the ctlc pin is; a ctlc pin current ?h? (i ctlch ). 5. 5 ctld pin current ?h? (i ctldh ), ctld pin current ?l? (i ctldl ) in the initial status, a current which flows in the ctld pin is the ctld pin current ?l? (i ctldl ). after that, increasing the ctld pin?s voltage gradually, the maximum current which flows in the ctld pin is; the ctld pin current ?h? (i ctldh ). 5. 6 sel pin current ?h? (i selh ), sel pin current ?l? (i sell ) in the initial status, a current which flows in the sel pin is the sel pin current ?h? (i selh ). after that, a current which flows in the sel pin when setting v sel = v ss is; the sel pin current ?l? (i sell ). 5. 7 cop pin leakage current (i coh ), cop pin sink current (i col ) start from the initial status, set v cop = v ss + 0.5 v, a current which flows in the cop pin is the cop pin sink current (i col ). after that, a current which flows in the cop pin when setting v1 = v2 = v3 = v4 = 5.5 v, v cop = v dd is; the cop pin leakage current (i coh ). 5. 8 dop pin source current (i doh ), dop pin sink current (i dol ) start from the initial status, set v dop = v ss + 0.5 v, a current which flows in the dop pin is the dop pin sink current (i dol ). after that, a current which flows in the dop pin when setting v1 = v2 = v3 = v4 = 1.8 v, v dop = v dd ? 0.5 v is; the dop pin source current (i doh ).
battery protection ic for 3-series or 4-series cell pack S-8204A series rev.2.2 _00 seiko instruments inc. 12 c 1 = 0.1 f v1 v2 v4 v3 a 1cop 2vmp 3dop 4vini 5 cdt 6 cct 7cit 8 16 vdd 15 vc1 14 vc2 13 vc3 12 vc4 11 ctlc ctld vss 9 S-8204A sel 10 figure 4 test circuit 1 c 1 = 0.1 f v1 v2 v4 v3 v v 1cop 2vmp 3dop 4vini 5 cdt 6 cct 7cit 8 16 vdd 15 vc1 14 vc2 13 vc3 12 vc4 11 ctlc ctld vss 9 S-8204A sel 10 a figure 5 test circuit 2 c 1 = 0.1 f v1 v2 v4 v3 1cop 2vmp 3dop 4vini 5 cdt 6 cct 7cit 8 16 vdd 15 vc1 14 vc2 13 vc3 12 vc4 11 ctlc ctld vss 9 S-8204A sel 10 v v a a a figure 6 test circuit 3
battery protection ic for 3-series or 4-series cell pack rev.2.2 _00 S-8204A series seiko instruments inc. 13 c 1 = 0.1 f v1 v2 v4 1cop 2vmp 3dop 4vini 5 cdt 6 cct 7cit 8 16 vdd 15 vc1 14 vc2 13 vc3 12 vc4 11 ctlc ctld vss 9 S-8204A sel 10 v v3 figure 7 test circuit 4 c 1 = 0.1 f v1 v2 v4 v3 a a a a a a a 1 cop 2 vmp 3 dop 4 vini 5 cdt 6 cct 7 cit 8 16 vdd 15 vc1 14 vc2 13 vc3 12 vc4 11 ctlc ctld vss 9 S-8204A sel 10 a a a figure 8 test circuit 5
battery protection ic for 3-series or 4-series cell pack S-8204A series rev.2.2 _00 seiko instruments inc. 14 ? operation remark refer to ? ? connection example of battery protection ic ?. 1. normal status in the S-8204A series, both of cop and dop pins get the v ss level; when all values of battery voltage are in the range of overdischarge detection voltage (v dln ) to overcharge detection voltage (v cun ), and due to the discharge or charge current, the vini pin?s volt age is in the range of charge overcurrent detection voltage (v ciov ) to discharge overcurrent detection voltage 1 (v diov1 ). this is the normal status. in addition, the charge/discharge fets are on. 2. overcharge status in the S-8204A series, when any voltage of the batteries increases to the level of v cun or more, the cop pin is set in high impedance. this is the overch arge status. the cop pin is pulled up to eb+ by an external resistor so that the charge fe t is turned off and it stops charging. this overcharge status is released if ei ther condition 1 or 2 is satisfied; (1) in case that the vmp pin voltage is set 39/40 v ds or more; all voltages of the batteries are in the level of overcharge release voltage (v cln ) or more. (2) in case that the vmp pin voltage is set 39/40 v ds or less; all voltages of the batteries are in the level of v cun or less. 3. overdischarge status in the S-8204A series, when any voltage of the batteries decreases to the level of v dln or less, the dop pin voltage gets the v dd level. this is the overdischarge stat us. the discharge fet is turned off and it stops discharging. this overdischarge status is released/maintained if either condition 1 to 3 is satisfied; (1) to release; the vmp pin voltage is in the v dd level or more, all voltages of the batteries are in the v dln level or more. (2) to release; the vmp pin voltage is v ds /2 or more and the vmp pin voltage is in the v dd level or less; all voltages of the batteries are in t he level of overdischarge release voltage (v dun ) or more. (3) the vmp pin voltage is v ds /2 or less, the S-8204A series maintains the power-down status. 4. power-down status in the S-8204A series, when it reaches the overdisc harge status, the vmp pin is pulled down to the v ss level by a resistor between vmp and vss pin (r vms ). if the vmp pin voltage decreases to the level of v ds /2 or less, almost every circuit in the S-8204A stops working so that the current consumption decreases to the level of current consumption at power down (i pdn ) or less. this is the power-down status. the power-down status is released if the following condition is satisfied. (1) the vmp pin voltage gets v ds /2 or more.
battery protection ic for 3-series or 4-series cell pack rev.2.2 _00 S-8204A series seiko instruments inc. 15 5. discharge overcurrent status in the S-8204A series, in batteries in the normal st atus, the discharging current increases more than a certain value. as a result, if the status in whic h the vini pin voltage increases to the level of v diov1 or more, the dop pin gets the v dd level. this is the discharge overcu rrent status. the discharge control fet is turned off and it stops discharging. this ic has three levels for discharge overcurrent detection (v diov1 , v diov2 , v short ). in the status of discharge overcurrent, the cop pin is set in hi gh impedance. the vmp pin is pulled up to the v dd level by a resistor between vmp and vdd pin (r vmd ). the S-8204A series? actions against discharge overcurrent detection voltage 2 (v diov2 ) and short circuit detection voltage (v short ) are as well in v diov1 . the status of discharge overcurrent is rele ased if the following condition is satisfied. (1) the vmp pin voltage gets v ds ? 1.2 v (typ.) or more. 6. charge overcurrent status in the S-8204A series, in batteries in the normal stat us, the charge current increases more than a certain value. as a result, if the status in which t he vini pin voltage decreases to the level of v ciov or less, the cop pin is set in high impedance. this is the charge overcurrent status. the charge control fet is turned off and it stops charging. in this charge overcurrent status, the vmp pin is pulled-up to the v dd level by r vmd . also in the overdischarge status, the function of charge overcurrent detection works. the status of charge overcurrent is releas ed if the following condition is satisfied. (1) the vmp pin voltage gets v ds or less. 7. 0 v battery charge function in this ic, regarding how to charge a discharged batte ry (0 v battery), users are able to select either function of the two mentioned below. (1) allow to charge a 0 v battery (enable to charge a 0 v battery) a 0 v battery is charged; when the voltage of a charger is charger voltage for start charging 0 v battery (v 0cha ) or more. (2) inhibit charging a 0 v battery (unable to charge a 0 v battery) a 0 v battery is not charged; when the voltage of a charger is battery voltage for inhibit charging 0 v battery (v 0inh ) or less. caution when the vdd pin voltage is less than the minimum value of operation voltage between vdd and vss pin (v dsop ), this ic?s action is not assured.
battery protection ic for 3-series or 4-series cell pack S-8204A series rev.2.2 _00 seiko instruments inc. 16 8. delay time setting in the S-8204A series, users are able to set delay ti me for the period; from detecting any voltage of the batteries or detecting changes in the voltage at the vi ni pin, to the output to the cop, dop pin. each delay time is determined by a resistor in the ic and an external capacitor. in the overchage detection, when any voltage of the batteries gets v cun or more, the s-8204 starts charging to the cct pin?s capacitor (c cct ) via the cct pin?s internal resistor (r inc ). after a certain period, the cop pin is set in high impedance if the voltage at the cct pin reaches t he cct pin detection voltage (v cct ). this period is overcharge detection delay time (t cu ). t cu is calculated using the following equation (v ds = v1 + v2 + v3 + v4). t cu [s] = ? ln ( 1 ? v cct / v ds ) c cct [ f] r inc [m ? ] = ? ln ( 1 ? 0.7 (typ.)) c cct [ f] 8.31 [m ? ] (typ.) = 10.0 [m ? ] (typ.) c cct [ f] overdischarge detection delay time (t dl ), discharge overcurrent detection delay time 1 (t diov1 ), discharge overcurrent detection delay time 2 (t diov2 ), charge overcurrent detection delay time (t ciov ) are calculated using the following equations as well. t dl [ms] = ? ln ( 1 ? v cdt / v ds ) c cdt [ f] r ind [k ? ] t diov1 [ms] = ? ln ( 1 ? v cit / v ds ) c cit [ f] r ini1 [k ? ] t diov2 [ms] = ? ln ( 1 ? v cit / v ds ) c cit [ f] r ini2 [k ? ] t ciov [ms] = ? ln ( 1 ? v cit / v ds ) c cit [ f] r ini1 [k ? ] in case c cct = c cdt = c cit = 0.1 [ f], each delay time t cu , t dl , t diov1 , t diov2 , t ciov is calculated as follows. t cu [s] = 10.0 [m ? ] (typ.) 0.1 [ f] = 1.0 [s] (typ.) t dl [ms] = 1000 [k ? ] (typ.) 0.1 [ f] = 100 [ms] (typ.) t diov1 [ms] = 200 [k ? ] (typ.) 0.1 [ f] = 20 [ms] (typ.) t diov2 [ms] = 20 [k ? ] (typ.) 0.1 [ f] = 2.0 [ms] (typ.) t ciov [ms] = 200 [k ? ] (typ.) 0.1 [ f] = 20 [ms] (typ.) short circuit detection voltage delay time (t short ) is fixed internally.
battery protection ic for 3-series or 4-series cell pack rev.2.2 _00 S-8204A series seiko instruments inc. 17 9. ctlc and ctld pins the S-8204A series has two pins to control. the ct lc pin controls the output voltage from the cop pin, the ctld pin controls the output voltage from the dop pin. thus it is possible for users to control the output voltages from the cop pin and dop pin i ndependently. these controls precede the battery protection circuit. table 5 conditions set by ctlc pin ctlc pin cop pin high *1 high-z open *2 high-z low *3 normal status *4 *1. high; ctlc v ctlch *2. pulled up by i ctlcl *3. low; ctlc v ctlch *4. the status is controlled by the voltage detection circuit. table 6 conditions set by ctld pin ctld pin dop pin high *1 v dd level open *4 v dd level low *2 normal status *3 *1. high; ctld v ctldh *2. pulled up by i ctldl *3. low; ctld v ctldl *4. the status is controlled by the voltage detection circuit. caution note that when the power supply fluctuates, unexpected behavior might occur if an electrical potential is generated between the potentials of ?l? level input to the ctlc/ctld pins and ic?s v ss by external filters r vss and c vss .
battery protection ic for 3-series or 4-series cell pack S-8204A series rev.2.2 _00 seiko instruments inc. 18 10. sel pin the S-8204A series has a pin to switch-control the protection for 3-cell or 4-cell battery. the overdischarge detection for v4-cell is inhibited by setti ng the sel pin ?l?, so that short-circuiting the v4 cell does not allow the overdischarge detection. this setting makes it possible to use the S-8204A series for 3-cell protection. the sel pin precedes the battery pr otection circuit. be sure to use the sel pin in ?h? or ?l?. table 7 protect conditions set by sel pin sel pin condition high *1 4-cell protection open indefinite low *2 3-cell protection *1. high; sel v selh *2. low; sel v sell in cascade connection, it is possible to use the s-82 04a series for protecting 6, 7 or 8-cell battery by combining the electrical level of sel pin. table 8 conditions set by sel pin in cascade connection sel pin in S-8204A (1) sel pin in S-8204A (2) condition low *1 low *1 6-series cell protection low *1 high *2 7-series cell protection high *2 high *2 8-series cell protection *1. low; sel v sell *2. high; sel v selh
battery protection ic for 3-series or 4-series cell pack rev.2.2 _00 S-8204A series seiko instruments inc. 19 ? timing chart (in the circuit in figure 12, 13) 1. overcharge detection and overdischarge detection (n = 1 to 4) v cun v dln v cln battery voltage v ss cop pin voltage dop pin voltage v ss charger connection load connection status *1 39/40 v dd v ss vmp pin voltage 1/2 v dd v dd v eb + v eb+ overcharge detection delay time (t cu ) <1> <2> <1> <3> <1> high-z overdischarge detection delay time (t dl ) v dd <4> *1. < 1 > : normal status < 2 > : overcharge status < 3 > : overdischarge status < 4 > : power-down status remark the charger is assumed to charge with a constant current. v eb + indicates the open voltage of the charger. figure 9
battery protection ic for 3-series or 4-series cell pack S-8204A series rev.2.2 _00 seiko instruments inc. 20 2. discharge overcurrent detection v cun v dun v dln (n = 1 to 4) v cln battery voltage v hc v hd v dd dop pin voltage v ss high-z v eb + v ss cop pin voltage v dd v ss vmp pin voltage v short v diov2 v ss vini pin voltage v dd v diov1 load connection status *1 discharge overcurrent detection delay time 1(t diov1 ) <1> <2> <1> <1> discharge overcurrent detection delay time 2 (t diov2 ) short circuit detection voltage delay time (t short ) <2> <1> <2> high-z high-z *1. < 1 > : normal status < 2 > : discharge overcurrent status remark the charger is assumed to charge with a constant current. v eb + indicates the open voltage of the charger. figure 10
battery protection ic for 3-series or 4-series cell pack rev.2.2 _00 S-8204A series seiko instruments inc. 21 3. charge overcurrent detection v cun v dun v dln (n = 1 to 4) v cln battery voltage v dd dop pin voltage v ss v eb + v ss cop pin voltage v dd v ss vmp pin voltage vini pin voltage v dd v diov1 charger connection status *1 v eb+ v ss v ciov v hc v hd <3> <2> <1> <1> high-z charge overcurrent detection delay time (t ciov ) <1> <2> charge overcurrent detection delay time (t ciov ) high-z <4> *1. < 1 > : normal status < 2 > : charge overcurrent status < 3 > : overdischarge status < 4 > : power-down status remark the charger is assumed to charge with a constant current. v eb + indicates the open voltage of the charger. figure 11
battery protection ic for 3-series or 4-series cell pack S-8204A series rev.2.2 _00 seiko instruments inc. 22 ? connection examples of battery protection ic 1. 3- series cell eb + r cop r vmp r dop r vini c cdt c cct eb ? 1cop 2vmp 3dop 4vini 5 cdt 6 cct 7cit 8 16 ctlc 15 vc1 14 vc2 13 vc3 12 vc4 11 ctld vdd vss 9 S-8204A r vc1 c vc2 c vc3 c vss c vc1 r vc3 r vss r sense ctlc sel 10 charging fet discharging fet r sel c cit r vc4 r ctlc ctld r ctld r vc2 figure 12 2. 4- series cell eb + r cop r vmp r dop r vini c cdt c cct eb ? 1cop 2vmp 3dop 4vini 5 cdt 6 cct 7cit 8 16 ctlc 15 vc1 14 vc2 13 vc3 12 vc4 11 ctld vdd vss 9 S-8204A r vc1 c vc2 c vc3 c vss c vc1 r vc3 r vss r sense ctlc sel 10 charging fet discharging fet r sel c cit r vc4 r ctlc ctld r ctld r vc2 c vc4 figure 13
battery protection ic for 3-series or 4-series cell pack rev.2.2 _00 S-8204A series seiko instruments inc. 23 3. 7- series cell eb + r cop r dop r vini1 c cdt1 c cct1 eb ? 1cop 2vmp 3dop 4vini 5 cdt 6 cct 7cit 8 16 ctlc 15 vc1 14 vc2 13 vc3 12 vc4 11 ctld vdd vss 9 S-8204A (1) r vc1 c vc2 c vc3 c vss1 c vc1 r vc3 r vss1 sel 10 charging fet discharging fet r cit1 r vc4 r vc2 r sel1 r inv3 r vini2 c cdt2 c cct2 1cop 2vmp 3dop 4vini 5 cdt 6 cct 7cit 8 16 ctlc 15 vc1 14 vc2 13 vc3 12 vc4 11 ctld vdd vss 9 r vc5 c vc6 c vc7 c vss2 c vc5 r vc7 r vss2 sel 10 c cit2 r vc8 r vc6 r sel2 r inv1 r ctld r ctlc m 6 r 2 r 3 r inv2 r 1 zd 1 d cop m 1 m 3 m 4 m 2 c eb + r eb + r ifc r ifd r sense m 5 c vc4 S-8204A (2) figure 14
battery protection ic for 3-series or 4-series cell pack S-8204A series rev.2.2 _00 seiko instruments inc. 24 table 9 constants for external components (in the circuits in figure 12, 13) symbol typical range unit r vc1 1 0.51 to 1 *1 k ? r vc2 1 0.51 to 1 *1 k ? r vc3 1 0.51 to 1 *1 k ? r vc4 1 0.51 to 1 *1 k ? r dop 5.1 2 to 10 k ? r cop 1 0.1 to 1 m ? r vmp 5.1 1 to 10 k ? r ctlc 1 1 to 10 k ? r ctld 1 1 to 10 k ? r vini 1 1 to 10 k ? r sel 1 1 to 100 k ? r sense ? 0 or higher m ? r vss 47 22 to 100 *1 ? c vc1 47 0 to 100 *1 nf c vc2 47 0 to 100 *1 nf c vc3 47 0 to 100 *1 nf c vc4 47 0 to 100 *1 nf c cct 0.1 0.01 or higher f c cdt 0.1 0.01 or higher f c cit 0.1 0.01 or higher f c vss 1 0 to 2.2 f *1. set up a filter constant to be r vss c vss = 47 f ? ? and to be r vc1 c vc1 = r vc2 c vc2 = r vc3 c vc3 = r vc4 c vc4 = r vss c vss . caution 1. the above constants may be changed without notice. 2. it is recommended that filter cons tants between vdd and vss should be set approximately to 47 f ? ? . e.g., c vss r vss = 1.0 f 47 ? = 47 f ? ? sufficient evaluation of transient power s upply fluctuation and overcurrent protection function with the actual application is needed to determine the proper constants. contact our sales office in case the constants should be set to other than 47 f ? ? . 3. it has not been confirmed whether the operation is normal in circuits other than the above example of connection. in addition, the example of connection shown above and the constants do not guarantee proper operation. perform thorough evaluation using an actual application to set the constant. ? precautions ? the application conditions for the input voltage, output voltage, and load curr ent should not exceed the package power dissipation. ? batteries can be connected in any order; however, there may be cases when discharging cannot be performed when a battery is connected. in such a case, short the vmp pin and vdd pin or connect the battery charger to return the ic to the normal mode. ? if both an overcharge battery and an overdischarge ba ttery are included among the whole batteries, the condition is set in overcharge status and overdischarg e status. therefore either charging or discharging is impossible. ? do not apply an electrostatic discharge to this ic that exceeds the performance ratings of the built-in electrostatic protection circuit. ? sii claims no responsibility for any disputes arisin g out of or in connection with any infringement by products including this ic of patents owned by a third party.
battery protection ic for 3-series or 4-series cell pack rev.2.2 _00 S-8204A series seiko instruments inc. 25 ? characteristics (typical data) 1. current consumption 1.1 i ope vs. v ds 1.2 i ope vs. ta 0 5 10 20 i ope [ a] 25 15 5 0 v ds [v] 35 15 30 20 10 22 40 i ope [ a] 25 15 5 0 35 30 20 10 40 ? 40 0 25 50 75 ta [ c] ? 25 85 1.3 i pdn vs. v ds 1.4 i pdn vs. ta 0 5 10 20 i pdn [ a] 0.07 0.05 0.03 0.00 v ds [v] 0.09 15 0.08 0.06 0.04 22 0.10 0.01 0.02 ? 40 0 25 50 75 ta [ c] ? 25 85 i pdn [ a] 0.07 0.05 0.03 0.00 0.09 0.08 0.06 0.04 0.10 0.01 0.02 2. overcharge detection / release voltage, overdischarge detection / release voltage, overcurrent detection voltage 2.1 v cu vs. ta 2.2 v cl vs. ta ? 40 0 25 50 75 ta [ c] ? 25 85 v cu [v] 4.360 4.350 4.340 4.325 4.370 4.365 4.355 4.345 4.375 4.330 4.335 ? 40 0 25 50 75 ta [ c] ? 25 85 v cl [v] 4.14 4.10 4.18 4.16 4.12 4.20 2.3 v du vs. ta 2.4 v dl vs. ta ? 40 0 25 50 75 ta [ c] ? 25 85 v du [v] 2.74 2.70 2.66 2.60 2.78 2.76 2.72 2.68 2.80 2.62 2.64 ? 40 0 25 50 75 ta [ c] ? 25 85 v dl [v] 2.02 1.98 1.94 2.06 2.04 2.00 1.96 2.08 1.92
battery protection ic for 3-series or 4-series cell pack S-8204A series rev.2.2 _00 seiko instruments inc. 26 2.5 v diov1 vs. v ds 2.6 v diov1 vs. ta 10 11 12 14 v diov1 [v] 0.27 0.25 0.23 0.20 v ds [v] 0.29 13 0.28 0.26 0.24 15 0.30 0.21 0.22 16 v diov1 [v] 0.27 0.25 0.23 0.20 0.29 0.28 0.26 0.24 0.30 0.21 0.22 ? 40 0 25 50 75 ta [ c] ? 25 85 2.7 v diov2 vs. v ds 2.8 v diov2 vs. ta 10 11 12 14 v diov2 [v] 0.54 0.50 0.46 0.40 v ds [v] 0.58 13 0.56 0.52 0.48 15 0.60 0.42 0.44 16 v diov2 [v] 0.54 0.50 0.46 0.40 0.58 0.56 0.52 0.48 0.60 0.42 0.44 ? 40 0 25 50 75 ta [ c] ? 25 85 2.9 v short vs. v ds 2.10 v short vs. ta 10 11 12 14 v short [v] 1.0 0.8 v ds [v] 1.2 13 1.1 0.9 0.7 15 1.3 16 ? 40 0 25 50 75 ta [ c] ? 25 85 v short [v] 1.0 0.8 1.2 1.1 0.9 0.7 1.3 2.11 v ciov vs. v ds 2.12 v ciov vs. ta 10 11 12 14 v ciov [v] v ds [v] 13 15 16 ? 0.08 ? 0.10 ? 0.12 ? 0.15 ? 0.06 ? 0.07 ? 0.09 ? 0.11 ? 0.05 ? 0.14 ? 0.13 ? 40 0 25 50 75 ta [ c] ? 25 85 v ciov [v] ? 0.08 ? 0.10 ? 0.12 ? 0.15 ? 0.06 ? 0.07 ? 0.09 ? 0.11 ? 0.05 ? 0.14 ? 0.13
battery protection ic for 3-series or 4-series cell pack rev.2.2 _00 S-8204A series seiko instruments inc. 27 3. cct pin internal resistance / detection voltage, cdt pin internal resistance / detection voltage, cit pin internal resistance / detection voltage and short circuit detection voltage delay time 3. 1 r inc ? ta 3. 2 v cct ? ta (v ds = 15.2 v) ? 40 0 25 50 75 r inc [m ? ] 9.0 6.0 ta [ c] 12.0 ? 25 85 7.0 8.0 10.0 11.0 ? 40 0 25 50 75 v cct [v] 10.7 10.4 ta [ c] 10.9 ? 25 85 10.5 10.6 10.8 3. 3 r ind ? ta 3. 4 v cdt ? ta (v ds = 12.0 v) ? 40 0 25 50 75 r ind [k ? ] 900 600 ta [ c] 1200 ? 25 85 700 800 1000 1100 ? 40 0 25 50 75 v cit [v] 9.6 ta [ c] 10.0 ? 25 85 9.7 9.8 9.9 3. 5 r ini1 ? ta 3. 6 v cit ? ta (v ds = 14.0 v) ? 40 0 25 50 75 r ini1 [k ? ] 180 120 ta [ c] 240 ? 25 85 140 160 200 220 ? 40 0 25 50 75 v cit [v] 9.6 ta [ c] 10.0 ? 25 85 9.7 9.8 9.9 3. 7 r ini2 ? ta 3. 8 t short ? ta ? 40 0 25 50 75 r ini2 [k ? ] 18.0 12.0 ta [ c] 24.0 ? 25 85 14.0 16.0 20.0 22.0 t short [ s] 300 500 400 200 600 ? 40 0 25 50 75 ta [ c] ? 25 85 0 100
battery protection ic for 3-series or 4-series cell pack S-8204A series rev.2.2 _00 seiko instruments inc. 28 4. cop / dop pin 4.1 i coh vs. v cop 4.2 i col vs. v cop 0 5 10 20 i coh [ a] 0.07 0.05 0.03 0.00 v cop [v] 0.09 15 0.08 0.06 0.04 22 0.10 0.01 0.02 0 3.5 7 14 i col [ma] 10 0 v cop [v] 20 10.5 15 5 25 4.3 i doh vs. v dop 4.4 i dol vs. v dop 0 1.8 3.6 7.2 i doh [ma] v dop [v] 5.4 3.5 2.5 1.5 0 4.5 4.0 3.0 2.0 5.0 0.5 1.0 0 3.5 7 14 i dol [ma] 10 0 v dop [v] 20 10.5 15 5 25

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the information described herein is subject to change without notice. seiko instruments inc. is not responsible for any problems caused by circuits or diagrams described herein whose related industrial properties, patents, or other rights belong to third parties. the application circuit examples explain typical applications of the products, and do not guarantee the success of any specific mass-production design. when the products described herein are regulated products subject to the wassenaar arrangement or other agreements, they may not be exported without authorization from the appropriate governmental authority. use of the information described herein for other purposes and/or reproduction or copying without the express permission of seiko instruments inc. is strictly prohibited. the products described herein cannot be used as part of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of seiko instruments inc. although seiko instruments inc. exerts the greatest possible effort to ensure high quality and reliability, the failure or malfunction of semiconductor products may occur. the user of these products should therefore give thorough consideration to safety design, including redundancy, fire-prevention measures, and malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.

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